Control store

A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. Early control stores were implemented as a diode-array accessed via address decoders, a form of read-only memory. This tradition dates back to the program timing matrix on the MIT Whirlwind, first described in 1947. Modern VLSI processors instead use matrices of field effect transistors to build the ROM and/or PLA structures used to control the processor as well as its internal sequencer in a microcoded implementation.

Writable stores

The original System/360 models of IBM mainframe had read-only control store, but later System/370 and successor models loaded their microprograms from floppy disks into a writeable control store consisting of ultra-high speed random-access read-write memory. This permitted IBM to easily repair microprogramming defects in the field. Even when the majority of the control store is stored in ROM of some sort, computer vendors often sell writeable control store as an option, allowing the customers to customize the machine's microprogram.

Timing, latching and avoiding a race condition

The control store usually has a register on its outputs. The outputs that go back into the sequencer to determine the next address have to go through some sort of register to prevent the creation of a race condition. In most designs all of the other bits also go through a register. This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle. This register is known as a pipeline register. Very often the execution of the next microinstruction is dependent on the result of the current microinstruction, which will not be stable until the end of the current microcycle. It can be seen that either way, all of the outputs of the control store go into one big register. Historically it used to be possible to buy EPROMs with these register bits on the same chip.

The clock signal determining the cycle time of the system primarily clocks this register.

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